quit -sim

set env(VIVADO_SIM)             F:/crack/vivado2017.4_questasim_10.6c_lib
vmap secureip                   $env(VIVADO_SIM)/secureip
vmap simprims_ver               $env(VIVADO_SIM)/simprims_ver
vmap unifast                    $env(VIVADO_SIM)/unifast
vmap unifast_ver                $env(VIVADO_SIM)/unifast_ver
vmap unimacro                   $env(VIVADO_SIM)/unimacro
vmap unimacro_ver               $env(VIVADO_SIM)/unimacro_ver
vmap unisim                     $env(VIVADO_SIM)/unisim
vmap unisims_ver                $env(VIVADO_SIM)/unisims_ver
vmap axis_infrastructure_v1_1_0     $env(VIVADO_SIM)/axis_infrastructure_v1_1_0
vmap axis_register_slice_v1_1_15    $env(VIVADO_SIM)/axis_register_slice_v1_1_15
vmap axis_dwidth_converter_v1_1_14  $env(VIVADO_SIM)/axis_dwidth_converter_v1_1_14

#工程所需要的文件
vlog -incr $env(VIVADO_SIM)/glbl.v;
vlog -sv -incr ../ip/stream_convert/sim/stream_convert.v
vlog -sv ../bench/axi4_stream_width_converter_sim.sv

#vlog +incdir+(UVM_SRC) -L mtiAvm -L mtiOvm -L mtiUvm -L mtiUPF hello_world.sv

vsim -t ps -voptargs="+acc" +notimingchecks \
                                    -L secureip \
                                    -L simprims_ver \
                                    -L unifast -L unifast_ver \
                                    -L unimacro -L unimacro_ver \
                                    -L unisim -L unisims_ver \
                                    -L axis_infrastructure_v1_1_0 \
                                    -L axis_register_slice_v1_1_15 \
                                    -L axis_dwidth_converter_v1_1_14    \
                                    work.axi4_stream_width_converter_sim

#vsim -t ns -novopt -sv_lib (UVM_DPI) work.hello_world_example 

log -r /*
radix 16

#view -title {wang} wave
#具体模块需要添加的信号
do wave.do

run 20us

